Selection circuit responsive to plural inputs in a priority sequence



3 Sheets-Sheet 2 R. N. MELLOTT- SELECTION CIRCUIT RESPONSIVE TO PLURAL INPUTS IN A PRIORITY SEQUENCE March 28, 1967 Filed July 18, 1963 FIJUNZO INVENTOR. ROBE/er N. 441211.077

A 77'0/2N5Y R. N. MELLOTT SELECTION CIRCUIT RESPONSIVE TO PLURAL INPUTS IN A PRIORITY SEQUENCE ,3 Sheets-Sheet :5

I T i l I l I l I l E 4 INVENTOR. ROBE 2'7" A M51407 {MM 4% A TTORNEV March 28, 1967 Filed July 18, 1963 United States Patent 3,311,881 SELECTION CIRCUIT RESPONSIVE TO PLURAL INPUTS IN A PRIORHTY SEQUENCE Robert N. Mellott, Los Angeles, Calif., assignor, by mesne assignments, to The Bunker-Rama Corporation, Stamford, Conn., a corporation of Delaware Filed July 18, 1963, Ser. No. 296,001 14 Claims. (Cl. 340-147) This invention relates generally to data processing apparatus and more particularly to a selection device for use with a plurality of binary elements, respectively arbitrarily numbered 1, 2, 3 N for seeking out and selecting the lowest numbered element in a given state and finds particular utility in monitoring a plurality of conductors.

For purposes of illustration and explanation, the invention herein will be described in connection with binary digital data processing apparatus but it is specifically pointed out that the term binary is used only in the sense that two different broad classes of manifestations are contemplated. For example, the two possible values of a binary manifestation can be respectively represented by the presence and absence of an electrical pulse but in addition the two values can be respectively represented by the presence and absence of an electrical pulse having predetermined and very precise characteristics.

In many diverse digital data processing systems, a bank of binary elements is provided with each element being connected to a different conductor so as to sense a binary signal therein, which can be manifested by the presence or absence of a pulse of a predetermined characteristic and can be representative of the occurrence or non-occurrence of a different condition. The binary element can be made to assume a true state, for example, in response to the presence of said pulse. It is often desired to be able to examine the respective states of the various elements at the end of a certain time interval in order to determine which elements were switched to the true state or alternatively which elements remained in the false state. Although straightforward commutation techniques can be used to sequentially sample each element, this procedure is often unnecessarily slow, particularly where the number of elements assuming the sought state is small compared to the total number of elements in the bank.

This latter situation often arises, for example, in the use of digital memories of the type disclosed in US Patent No. 3,031,650 which can appropriately be considered a content addressable memory inasmuch as its storage locations are addressed or selected on the basis of the contents stored therein rather than on the basis of some arbitrarily assigned address. Such a memory permits all of the memory storage locations to be simultaneously searched to determine whether any of the words stored therein are identical to a search word being sought. A different word line is associated with all of the storage elements of each storage location and for each bit of any stored word which mismatches the corresponding bit of the search word, a pulse is provided on the word line associated with the location containing the dissimilar bit. (Of course, in an alternative embodiment, pulses can be provided to represent a match situation.) Each word line can have a different binary element connected thereto which can be switched to a true state in response to the presence of one or more pulses on the associated word line. At the end of a search period, it is desirable to examine all elements to determine which ones, if any, remained in the false state. A binary element remaining in the false state would of course indicate that all of the bits stored in the associated storage location are respectively identical to the corresponding bits of the search word. In addition to merely determining which binary elements "ice remained in the false state, it is sometimes desirable to make these determinations sequentially in order to permit this information to be conventionally utilized to subsequently read out, write in, or modify the same or other information in the same or another memory.

Inasmuch as the number (M) of binary elements remaining in the false state for most contemplated applications of a content addressable memory will be extremely small compared to the number (N) of binary elements which are switched to the true state, it is desirable to avoid the utilization of conventional time consuming com-mutation techniques to sequentially sample each of the elements.

In view of this, it is an object of the present invention to provide a selection device for use with a plurality of binary elements respectively arbitrarily numbered 1, 2, 3 N for seeking out and selecting the lowest numbered element in a given state.

More particularly, it is an object of this invention to provide such a selection device which can select the lowest numbered element in a given state in the same finite time period regardless of which particular element is in fact the lowest numbered element in said given state.

It is a still further object of this invention to provide such a selection device which can sequentially select each of the M binary elements, of a total number of N binary elements, in a given state in M finite time periods regardless of which M elements are in said given state.

It is a still further object of this invention to provide such a selection device including a number (P) of segments connected in tandem, each segment including N/ P binary elements, such that in addition to each of the M binary elements in a given state being sequentially selected, each of the segments containing any binary elements in said given state is sequentially selected.

To a great extent the above objects are achieved by an invention disclosed in U.S. patent application Ser. No. 296,053, entitled, Selection Device, filed on July 18, 1963, by Ralph I. Koerner and Edward I. Schneberger and assigned to the same assignee as this present application. The invention disclosed herein presents a different and unique hardware approach from that disclosed in the Koerner et a1. application to arrive at functionally similar results.

Briefly, the invention herein is based on the recognition that current can be steered out of a series circuit comprised of a plurality of similarly poled unidirectional current conducting elements respectively defining circuit junctions betwen adjacent elements and into only one of a plurality of taps respectively connected to the circuit junctions. Each tap is biased by a different binary element, by establishing a voltage between adjacent taps, responsive to conduction through one of the taps, which is insufficient to forward bias the unidirectional element therebetween.

In a preferred embodiment of the invention, a series circuit including N stages, each stage including a diode, is connected between a positive potential source and ground to permit current to be driven through the similarly poled diodes. A tap is connected to the anode of each of the diodes in the series circuit. A different transistor switch is respectively connected to each of the taps. Each transistor switch is in turn biased by a different one of a plurality of binary elements. When the binary elements are in a first or false state, the transistor switches are so biased as to tend to permit current flow therethrough from the series circuit through the tap to which it is connected. On the other hand, when the binary elements are in a second or true state, they respectively off bias the transistor switches to which they are connected.

A current diverted through any one of the taps establishes the potential of the anode to which it is connected slightly above ground. Since the cathode of the same stage is connected to the anode of the next stage (i.e., further displaced from the positive potential source) which may also have a tap connected to a forward biased transistor switch, the potential difference between the anode and cathode of the stage through which the current is diverted is not sufiicient to forward bias the diode and consequently substantially no current enters the tap of the next stage.

The current diverted through the one tap and its associated transistor switch constituting an output circuit can be utilized to write in or read out information into a content addressable memory or some other memory. On the other hand, it can be used merely to a appropriately energize an encoding circuit to generate signals representative of an address code identifying the selected binary element. In addition to finding utility for such external functions, the diverted current can be utilized to appropriately steer an advance pulse applied to all of the binary elements to cause only the selected binary element to be switched to its second state. As a consequence of switching the selected binary element to a second state, the current in the series circuit will then be diverted through the tap connected to the next stage. In this manner, M binary elements in a given state of a total number of N such elements can be sequentially selected in M finite time periods.

Although the selection device disclosed herein finds particular utility in conjunction with content addressable memories, it additionally can be advantageously employed wherever a plurality of conductors, on which signals having predetermined characteristics can randomly appear, are to be monitored. For example only, the selection device can be used to monitor a plurality of telephone lines which are randomly and possibly simultaneously energized.

The novel features that are considered characteristic of this invention are set forth with particularity in the appended claims. The invention itself both as to its organization and method of operation, as well as additional objects and advantages thereof, will best be understood from the following description when read in connection with the accompanying drawings, in which:

FIGURE 1 is a schematic diagram of a plurality of stages of a selection device constructed in accordance with the present invention;

FIGURE 1a illustrates a characteristic curve of a conventional diode;

FIGURE 2 is a schematic diagram illustrating the manner in which a plurality of selection device segments can be cascaded; and

FIGURE 3 is a schematic diagram illustrating the manner in which a plurality of selection device segments can be cascaded such that those segments containing no binary elements in a given state are bypassed in a sequential consideration of the segments.

Attention is now called to FIGURE 1 which schematically illustrates the selection device constructed in accordance with the present invention. As previously pointed out, it is often desirable, as in the use of content addressable memories, to be able to detect the presence or absence of pulses on conductors and then in response to such detected information provide output signals for performing different tasks.

Assume for example that each of a plurality of conductors (respectively arbitrarily numbered 10 10 10 constitutes a word line of a content addressable memory (not shown). In accordance with the previously mentioned US. Patent 3,031,650, pulses are provided on the respective word lines when bits stored in the locations associated with the word lines are not identical with corresponding bits of a search word. The selection device herein is provided to select those conductors 10 on which no pulses appear and subsequently provide signals to perform different operations in accordance with whichever conductors were selected. The selection device includes a plurality of stages N equal in number to the number of conductors 10. Inasmuch as all of the stages are substantially identical, a detailed discussion will be directed only toward stage 1 and its relationship with the other stages.

Stage 1 includes a binary element, in this case a bistable element, comprising a flip-flop circuit including transistors Q1 and Q2. The emitters of each of transistors Q1 and Q2 are grounded. The base of transistor Q1 is connected to conductor 10 while the base of transistor Q2 is connected directly to the collector of transistor Q1 and through a resistor R3 to a source of positive potential (-l-E). The collector of transistor Q2 is connected through a resistor R4 to the source of positive potential (+E) and through a resistor R2 to the base of transistor Q1. The base of transistor Q1 is additionally connected through a resistor R1 to a source of negative potential (E).

In addition to the transistors Q1 and Q2 comprising the bistable circuit, transistors Q3 and Q4 are provided. The collector of transistor Q3 is connected to the collector of transistor Q1 while the emitter thereof is connected directly to an advance pulse source 12, the purpose of which will be set forth hereafter. The base of transistor Q3 is connected through a capacitor C1 to ground and through a resistor R5 to a source of negative potential (-E). The base of transistor Q4, is connected to the collector of transistor Q2 while the collector of transistor Q4 is connected through resistor R5 to a source of negative potential (E). The emitter of transistor Q4 is connected to a tap T which in turn is connected to the anode of a diode D As will be more readily appreciated below, the tap and emitter-collector path of transistor Q4 can be considered to comprise an output circuit controllable by the bistable circuit to which it is connected.

Diode D is connected in a series circuit which includes one diode from each of the stages. A positive potential source, nominally shown as volts, is connected through a resistor 14 to the anode of the diode D of stage 1. The cathode of the diode D is in turn connected to the anode of the diode D of stage 2, the cathode of the diode D to the anode of the diode D etc. The cathode of the diode D of stage N is connected to ground.

Attention is momentarily called to FIGURE la which illustrates a typical characteristic curve of each of the diodes. Note that for a small voltage drop across a diode, that is below about 0.6 volt, the current through the diode is extremely small. On the other hand, when the voltage drop exceeds 0.6 volt, the current through the diode increases very rapidly. Although an appreciation of this characteristic is extremely significant to an understanding of the operation of this invention, it is to be understood that the quantitative value of 0.6 volt is not significant and the invention could function equally as well if the knee of the diode characteristic resided at some other voltage level.

In order to understand the operation of the invention, let it be initially assumed that the bistable elements in each stage are in a false state, i.e., with the transistors Q1 cut off and the transistors Q2 conductive. Let it then be assumed that the content addressable memory (not shown) performs a search and as a consequence a pulse is generated on conductor 10 but that no pulses are generated on conductors 10 and 10 In accordance with the previous explanation, this should be understood to mean that the bit pattern stored in the content addressable memory location associated with the conductor 1%; was not identical to the search word being sought, while the bit patterns stored in the locations associated with conductors 10 and 10 were identical to the search word.

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The pulse on line IO will forward bias transistor Q1 of stage N and as a result lower the potential on the base of transistor Q2 of stage N. As a consequence, transistor Q2 will be biased off. This action in turn causes the potential +5, to be applied to the base of transistor Q4 of stage N which will accordingly be biased off.

On the other hand, inasmuch as no pulses appeared on conductors 1G and 1& transistors Q2 of stages 1 and 2 will respectively remain conductive. As a consequence, current I tends to fiow from. the +100 volt source connected to resistor 14 through transistors Q4 of both stages 1 and 2. Instead of the current I in resistor 14 flowing into transistors Q4 of both stages I and 2 however, substantially all of it will flow into transistor Q4 of stage 1 with no more than negligible amounts entering stage 2. That substantially all of current I will be restricted to stage 1 can be readily understood when it is realized that the potentials established at the emitters of transistors Q4 of both stages 1 and 2 will be equal to the sum of the emitter-base voltage drops of transistors Q4 and the collector-emitter voltage drops of transistors Q2 which will be slightly above ground potential. Inasmuch as the cathode of the diode D is connected to the emitter of transistor Q4 of stage 2, it becomes apparent that the voltage drop across the diode D will remain below 0.6 volt. Inasmuch as the diode characteristic in FI"- URE la clearly indicates that substantially no current is conducted through the diode when the forward voltage drop thereacross in below 0.6 volt, it follows that substantially the full current I will enter the emitter of transistor Q4 of stage 1.

The critical concept regarding the steering of the current I lies in the substantially identical characteristics of the transistors Q2 and Q4 of stages l and 2. In the worst case, that is when both the emitter-base voltage drop of transistor Q4 of stage I and the collector-emitter voltage drop of transistor Q2 of stage 1 are a maximum and both the emitter-base voltage drop of transistor Q4 of stage 2 and the collector-emitter voltage drop of transistor Q2 of stage 2 are a minimum, proper current steering will occur so long as the sum. of the maximum voltage drops exceeds the sum of the minimum voltage drops by less than 0.6 volt. Consequently, realizing that the current steering scheme described operates satisfactorily when transistors Q2 are conductive in adjacent stages, it should be apparent that the steering will work even \better when the stages in which transistors Q2 are conductive are separated by stages in which transistors Q2 are not conductive. This is so because an integral multiple of 0.6 volt drops would be necessary to forward bias all the diodes between conductive stages.

If desired, instead of connecting the cathode of the diode of stage N to ground, it could be connected to a negative potential source in order to force a small amount of current through the series circuit to thereby bias the diodes so as to effectively shift the characteristic curve of FIGURE la slightly closer to the vertical or current axis. This will slightly change the steering criterion. That is, instead of it merely being necessary that the maximum voltage drops across transistors Q2 and Q4 of stage it be less than 0.6 volt greater than the minimum voltage drops across transistors Q2 and Q4 of stage 2, it may be necessary that the maximum voltage drops be no greater than, for example, 0.3 volt great than the minimum voltage drops.

When current I is diverted from the series diode circuit into one of the taps, it will saturate the transistor Q4 connected to the tap and consequently raise the potential of the collector of transistor Q4 and the output line 16 connected thereto to substantially ground. Thus, the transistor Q4 collector voltage can be used to initially identify the first or lowest numbered conductor lltl on which no pulse appeared. Each of the output lines 16 can drive an encoder network 17 to thereby generate ad dress signals identifying a particular conductor.

To sequentially generate address code signals identifying all the conductors 10 on which no pulse appeared, use can be made of the advance pulse source connected to the emitter of transistor Q3. The generation of a negative advance pulse by source 12 forward biases transistor Q3 of the stage in which transistor Q4 is conducting since the collector potential of the conductive transistor Q4 will be at ground level. It should be clear that all other transistors Q3 will be off biased inasmuch as the collectors of all non-conductive transistors Q4 will reside at substantially -E.

Conduction of transistor Q3 effectively deprives transistor Q2 of base current and consequently off biases transistor Q2, thereby on biasing transistor Q1. The capacitor C1 is provided to prevent the development of a race condition which might permit the bistable elements of two stages to be reset during the same advance pulse. By connecting the capacitor C1 between the base of transistor Q3 and ground, the base voltage of transistor Q3 is prevented from changing extremely fast in both the stage in which transistor Q4 is presently conducting and the stage in which conduction will subsequently be initiated. Use of the capacitor C1 therefore somewhat relieves the critical nature of the duration of the advance pulse.

In order to further avoid a race condition from developing, the +l00-volt source could be disconnected from the series diode circuit for the duration in which the advance pulse is being applied to the transistors Q3. The capacitor Cll of the stage in which transistor Q4 had been previously conducting will be sufliciently charged to forward bias the transistor Q3 when the advance pulse is applied even in the absence of current I flowing through transistor Q4.

From the foregoing, it should be appreciated that a selection device has herein been disclosed which permits current to be steered in accordance with the states of bistable elements so as to permit coded address signals to be generated identifying only one, arbitrarily the lowest numbered, of a plurality of bistable elements in a given state. Additionally, it has been shown that by properly applying an advance pulse to all of the stages of the selection device, coded address signals can be sequentially generated to thereby sequentially identify all of the bistable elements in a given state.

From the nature of the current steering previously described, it should be apparent that a very definite upper limit exists regarding the number of stages that can be interconnected in the manner shown in FIGURE 1. More particularly, if N is too large a number, when current I is being conducted through transistor Q4 of stage N, there may be a sufilcient voltage build-up across the diodes of all of the stages to thereby forward bias transistor Q4 of stage 1 even if transistor Q2 of that stage were not conducting. In order to prevent such an occurrence, it is essential that the number of diodes connected together in the same series circuit be limited.

For example, by establishing the upper limit of N at 116, the potential at tap T is restricted to a variation between approximately 0 and 10 volts. This permits the potential +E at the collector of transistor Q2 to be easily established at a high enough value to assure that transistor Q4 of stage 1 remains nonconductive when transistor Q4 of stage N conducts. Additionally, the relatively small voltage excursion range at tap T assures that current I remains substantially constant regardless of which stage conducts.

Where the number N is large, instead of connecting the diodes of all of the stages in a single series circuit, the stages can be segmented into P segments such that each of the segments will include N/P stages. As shown in FIGURE 2, adjacent segments can then be interconnected by the utilization of a coupling circuit including transistors Q5 and Q6. For example, in the coupling circuit of segment 1, the collector of transistor Q5 and the base of transistor Q6 are connected through a resistor 22 to a source of positive potential (i-E). The emitters of transistors Q and Q6 are grounded and the collector of transistor Q6 is connected to the resistor 14 of segment 2. The base of transistor Q5 is connected to the cathode of stage N/P of segment 1 and through resistor 20 to a negative potential source (E). So long as current I is being diverted through any of the taps connected to the series circuit of segment 1, the potential on the base of transistor Q5 will be below ground and accordingly transistor Q5 will be off biased. As a consequence, the base of transistor Q6 will be positive and the transistor will be forward biased so as to draw all of the current from resistor 14 of segment 2 therethrough. More particularly, when transistor Q6 of segment 1 is conductive, current I is prevented from being diverted from the series circuit of segment 2 into any of the taps connected thereto. On the other hand, if current I is not diverted into any of the taps in segment 1 and instead flows through resistor 20, the potential established on the base of transistor Q5 of segment 1 will be sufficiently positive to forward bias transistor Q5 and as a consequence off bias transistor Q6 to thereby cause current I to be applied to the series diode circuit of segment 2.

Inasmuch as the number of segments utilized may be large and the number of conductors 10 upon which no pulse appears may be small, a technique is illustrated in FIGURE 3 for interconnecting segments so as to eliminate the current propagation time through the series diode circuit of segments whose bistable elements all have been switched to a true state, that is where transistor Q1 is conducting. More particularly, a transistor Q7 is connected between segments with the emitter thereof being connected through a resistor 30 to a negative potential. The collector of transistor Q7 is connected to a positive potential source while the base of transistor Q7 is connected through a resistor 32 to a positive potential source, through a diode 34 to the emitter of a transistor Q7 of a previous segment, and to a diode 36 which in turn is connected through a plurality of diodes 38 each of which is connected to the bistable element in a different stage. More particularly, the cathodes of diodes 38 can be respectively connected to the collectors of different transistors Q2.

In operation, when the base of transistor Q7 of segment 2 is at a high potential, a substantial amount of current will be conducted therethrough and as a consequence, its emitter voltage will be at a positive potential thereby allowing current I through the series diode circuit of segment 3. On the other hand, when the base of transistor Q7 of segment 2 is at a low potential, its emitter will be at a much lower potential and current I will not flow through the series diode circuit of segment 3 but instead will be driven through the resistor 30 of segment 2.

It is apparent that so long as any bistable element in a segment is in a false state, current conduction through the series diode circuit of a subsequent segment should be prevented. However, when all the bistable elements of a segment are in a true state, the current I should be driven through the series diode circuit of the subsequent segment only if bistable elements in a false state exist therein. 7

Assume that address code signals identifying the last bistable element in a false state in the segment 1 have just been generated and as a consequence a positive voltage is applied to the base of transistor Q7 of segment 1. Consequently, a positive potential will be applied to the cathode of diode 34 of segment 2. If all of the bistable elements in segment 2 are in their true state, that is with transistor Q1 conducting and the collector of transistor Q2 at a high potential, transistor Q7 of segment 2 will be caused to immediately conduct heavily regardless of the amount of time it takes the current I to propagate through the series diode circuit of segment 2. On the other hand, then assume that at least one of the bistable elements of segment 3 is in a false state, that is with transistor Q2 conducting so that its collector is at a low voltage level. As a consequence, the emitter of transistor Q7 of segment 3 will remain at a low voltage level until the false bistable element in segment 3 is switched to a true state. So long as the emitter of transistor Q7 is at a low voltage level, the current I is prevented from flowing in the series diode circuit of segment 4.

From the foregoing, it should be apparent that a selection device has been provided herein which enables each of M bistable elements in a given state, of a total number of N such elements, to be selected in M finite time periods.

The embodiments of the invention in which an exclusive property of privilege is claimed are defined as follows:

1. In combination with a plurality of binary elements each capable of assuming either a first or second state and each respectively arbitrarily numbered 1, 2, 3 N, each element having a different output circuit associated therewith, selection means for initiating current in the output circuit associated with the lowest numbered binary element assuming said first state, said selection means comprising:

a series circuit including a plurality of similarly poled unidirectional current conducting elements respectively arbitrarily numbered 1, 2, 3 N;

a voltage source connected to said series circuit for driving a current therethrough; each of said output circuits including a tap each of which is connected to a corresponding terminal of a different one of said unidirectional elements;

means connecting each of said binary elements to the tap connected to said corresponding terminal of a correspondingly numbered unidirectional element;

means tending to divert current from said series circuit into said taps connected to binary elements in said first state; and

means responsive to current diverted into any one of said taps for establishing a potential at that tap insufficient to forward bias the unidirectional element connected thereto.

2. In combination with a plurality of binary elements each capable of assuming either a first or second state and each respectively arbitrarily numbered 1, 2, 3 N, each element having a different output circuit associated therewith, selection means for initiating current in the output circuit associated with the lowest numbered binary element assuming said first state, said selection means comprising:

a series circuit including a plurality of similarly poled diodes respectively arbitrarily numbered 1, 2, 3

a positive potential source;

a negative potential source;

means connecting the anode of said lowest numbered diode to said positive potential source and the cathode of said highest numbered diode to said negative potential source;

each of said output circuits including a tap each respectively connected to the anode of a different one of said diodes;

means respectively connecting each of said binary elements to the tap connected to the anode of a correspondingly numbered diode; means for establishing a current path from said positive potential source through the taps respectively connected to said binary elements in said first state; and

means responsive to current through any one of said taps for back biasing the diode whose anode is connected thereto.

3. In combination with a plurality of binary elements each capable of assuming either a first or second state and each respectively arbitrarily numbered 1, 2, 3 N, each element having a different output circuit associated therewith, selection means for initiating current in the output circuit associated with the lowest numbered binary element assuming said first state, said selection means comprising:

a series circuit including a plurality of similarly poled diodes respectively arbitrarily numbered 1, 2, 3

a positive potential source;

a negative potential source;

- means connecting the anode of said first lowest numbered diode to said positive potential source and the cathode of said highest numbered diode to said negative potential source;

each of said output circuits includin a tap each respectively connected to the anode of a different one of said diodes;

a plurality of switches each of which is connected to a different one of said taps;

means respectively connecting each of said binary elements to the switch connected to the anode of a correspondingly numbered diode for respectively closing each of said switches in response to a first state of the binary element to which it is connected; and

means responsive to current through any one of said taps for establishing a potential at that tap insufficient to forward bias the diode whose anode is connected thereto.

4. The combination of claim 3 wherein each of said switches comprises a transistor having a base, a collector and an emitter;

each of said binary elements being respectively connected to the base of a different one of said transistor; and

each of said emitters being respectively connected to a different one of said taps.

5. In combination with a plurality of conductors respectively arbitrarily numbered 1, 2, 3 N, on which pulses can randomly appear, means responsive to said pulses for recording their appearance and for subsequently initiating current in an output circuit uniquely associated with the lowest numbered conductor on which no pulses appeared, said means comprising:

a plurality of binary elements respectively arbitrarily numbered 1, 2, 3 N each of which is connected to a correspondingly numbered conductor, and responsive to the application of a pulse thereto for assuming a second state;

a series circuit including a plurality of similarly poled diodes respectively arbitrarily numbered 1, 2, 3

means for driving a current in the forward direction through said series circuit;

a plurality of output circuits each including a tap re spectively connected to the anode of a different one of said diodes;

means respectively connecting each of said binary elements to the tap connected to the anode of a correspondingly numbered diode;

means tending to divert current from said series circuit into said taps connected to binary elements in said first state; and

first means responsive to current diverted into any one of said taps for establishing a potential at that tap insufficient to forward bias the diode whose anode is connected thereto.

6. The combination of claim 5 wherein each of said binary elements comprises a flip-flop circuit including first and second transistors;

means interconnecting said first and second transistors for inhibiting conduction in said first transistor when said second transistor is conducting and for inhibiting conduction in said second transistor when said first transistor is conducting;

said means respectively connecting each of said binary elements to a different one of said taps comprising respective transistor switches; and

means connecting the collector of each of said first transistors to the base of a different one of said transistor switches.

7. In combination with a plurality of conductors respectively arbitrarily numbered 1, 2, 3 N, on which pulses can randomly appear, means responsive to said pulses for recording their appearance and for subsequently sequentially generating coded signals identifying those conductors on which no pulses appeared, said means com prising:

a plurality of bistable elements respectively arbitrarily numbered 1, 2, 3 N each of which is connected to a correspondingly numbered conductor, and responsive to the application of a pulse thereto for a suming a second state;

a series circuit including a plurality of similarly poled diodes respectively arbitrarily numbered 1, 2, 3 N;

means for driving a current in the forward direction through said series circuit;

a plurality of taps each respectively connected to the anode of a different one of said diodes;

means respectively connecting each of said bistable elements to the tap connected to the anode of a correspondingly numbered diode;

means tending to divert current from said series circuit into said taps connected to bistable elements in said first state;

first means responsive to current diverted into any one of said taps for establishing a potential at that tap insufficient to forward bias the diode whose anode is connected thereto; and

second means responsive to current diverted into any one of said taps for generating coded signals identifying the number of the bistable element, and consequently the number of the conductor, to which it is connected. 8. In combination with a plurality of conductors respectively arbitrarily numbered 1, 2, 3 N, on which pulses can randomly appear, means responsive to said pulses for recording their appearance and for subsequently sequentially initiating current in a plurality of output circuits each uniquely associated with one of said conductors on which no pulses appeared, said means comprising:

a plurality of bistable elements respectively arbitrarily numbered 1, 2, 3 N each of which is connected to a correspondingly numbered conductor, and responsive to the application of a pulse thereto for assuming a second state;

a series circuit including a plurality of similarly poled diodes respectively arbitrarily numbered 1, 2, 3 N;

means for driving a current in the forward direction through said series circuit;

a plurality of output circuits each including a tap respectively connected to the anode of a ditferent one of said diodes;

means respectively connecting each of said bistable elements to the tap connected to the anode of a correspondingly numbered diode;

means tending to divert current from said series circuit into said taps connected to bistable elements in said first state;

first means responsive to current diverted into any one of said taps for establishing a potential at that tap insufficient to forward bias the diode whose anode is connected thereto;

means for applying an advance pulse to each of said bistable circuits; and

second means responsive to current diverted into any one of said taps for switching the bistable element connected thereto to said second state in response to the application of said advance pulse.

9. In combination with a plurality of conductors respectively arbitrarily numbered 1, 2, 3 N, on which pulses can randomly appear, means responsive to said pulses for recording their appearance and for subsequently sequentially initiating current in a plurality of output circuits each uniquely associated with one of said conductors on which no pulses appeared, said means comprising:

a plurality of bistable elements respectively arbitrarily numbered 1, 2, 3 N each of which is connected to a correspondingly numbered conductor, and responsive to the application of a pulse thereto for assuming a second state;

a first series circuit including a first plurality of similarly poled diodes respectively arbitrarily numbered 1, 2 N/2;

a second series circuit including a second plurality of similarly poled diodes respectively arbitrarily numbered N/2+l, N/2+2 N;

means for driving a current in the forward direction through each of said series circuits;

a plurality of output circuits each including a tap respectively connected to the anode of a different one of said diodes;

means respectively connecting each of said bistable elements to the tap connected to the anode of a correspondingly numbered diode;

means tending to divert current from each of said series circuits into the taps respectively connected thereto which are also connected to bistable elements in said first state;

first means responsive to current diverted into any one of said taps for establishing a potential at that tap insufficient to forward bias the diode whose anode is connected thereto;

means for applying an advance pulse to each of said bistable elements;

second means responsive to current diverted into any one of said taps for switching the bistable element connected thereto to said second state in response to the application of said advance pulse; and

means for inhibiting current in said second series circuit so long as one of said bistable elements connected to said first series circuit is in said first state.

10. The combination of claim 9 wherein each of said bistable elements comprises a flip-flop circuit including first and second transistors;

means interconnecting said first and second transistors for inhibiting conduction in said first transistor when said second transistor is conducting and for inhibiting conduction in said second transistor when said first transistor is conducting;

said means respectively connecting each of said bistable elements to a different one of said taps comprising respective transistor switches; and

means connecting the collector of each of said first transistors to the base of a different one of said transistor switches.

11. The combination of claim 10 wherein said means for inhibiting current in said second series circuit includes a coupling circuit including first and second coupling transistors;

means connecting the collector of said second coupling transistor to said second series circuit;

means connecting the base of said first coupling transistor to said first series circuit for off biasing said first coupling transistor in response to the existence of bistable elements in said first state connected to said first series circuit; and

means interconnecting said first and second coupling transistors for forward biasing said second coupling transistor when said first coupling transistor is off biased. 12. In combination with a plurality of conductors respectively arbitrarily numbered 1, 2, 3 N, on which pulses can randomly appear, means responsive to said pulses for recording their appearance and for subsequently sequentially initiating current in a plurality of output circuits each uniquely associated with one of said conductors on which no pulses appeared, said means comprising:

a plurality of bistable elements respectively arbitrarily numbered 1, 2, 3 N each of which is connected to a correspondingly numbered conductor, and responsive to the application of a pulse thereto for assuming a second state;

a plurality of series circuits respectively arbitrarily numbered 1, 2, P each of which respectively includes a plurality of similarly poled diodes respectively arbitrarily numbered 1, 2, NH and N/P+l 2N/P and 2N/P+l 3N/P and (Pl)N/P+1 N;

means for driving a current in the forward direction through each of said series circuits;

a plurality of output circuits each including a tap respectively connected to the anode of a different one of said diodes;

means respectively connecting each of said bistable elements to the tap connected to the anode of a correspondingly numbered diode;

means tending to divert current from each of said series circuits into the taps respectively connected thereto which are also connected to bistable elements in said first state;

first means responsive to current diverted into any one of said taps for establishing a potential at that tap insufiicient to forward bias the diode whose anode is connected thereto;

means for applying an advance pulse to each of said bistable elements;

second means responsive to current diverted into any one of said taps for switching the bistable element connected thereto to said second state in response to the application of said advance pulse;

means for inhibiting current in any series circuit so long as one of said bistable elements connected to a lower numbered series circuit is in said first state; and

means for inhibiting current in any series circuit so long as no bistable element connected thereto is in said first state.

13. The combination of claim 12 wherein each of said bistable elements comprises a flip-flop circuit including first and second transistors;

means interconnecting said first and second transistors for inhibiting conduction in said first transistor when said second transistor is conducting and for inhibiting conduction in said second transistor when said first transistor is conducting;

said means respectively connecting each of said bistable elements to a different one of said taps comprising respective transistor switches; and

means connecting the collector of each of said first transistors to the base of a different one of said transistor switches.

14. The combination of claim 13 wherein said means for inhibiting current includes a plurality of coupling transistors, each respectively connected to each of said series circuits;

means connecting the base of each of said coupling transistors to a potential source for normally forward biasing said coupling transistors;

means responsive to the existence of a bistable element in said first state connected to the series circuit of each of said respective coupling transistors or to a lower numbered series circuit for back biasing said respective coupling transistors; and

means connecting each of said coupling transistors to a succeedingly higher numbered series circuit for inhibiting current in said higher numbered series circuit when said coupling transistor is back biased.

No references cited. NEIL C. READ, Primary Examiner. H. PIIT S, Assistant Examiner. 

1. IN COMBINATION WITH A PLURALITY OF BINARY ELEMENTS EACH CAPABLE OF ASSUMING EITHER A FIRST OR SECOND STATE AND EACH RESPECTIVELY ARBITRARILY NUMBERED 1,2,3...N, EACH ELEMENT HAVING A DIFFERENT OUTPUT CIRCUIT ASSOCIATED THEREWITH, SELECTION MEANS FOR INITIATING CURRENT IN THE OUTPUT CIRCUIT ASSOCIATED WITH THE LOWEST NUMBERED BINARY ELEMENT ASSUMING SAID FIRST STATE, SAID SELECTION MEANS COMPRISING: A SERIES CIRCUIT INCLUDING A PLURALITY OF SIMILARLY POLED UNIDIRECTIONAL CURRENT CONDUCTING ELEMENTS RESPECTIVELY ARBITRARILY NUMBERED 1, 2, 3 ... N; A VOLTAGE SOURCE CONNECTED TO SAID SERIES CIRCUIT FOR DRIVING A CURRENT THERETHROUGH; EACH OF SAID OUTPUT CIRCUITS INCLUDING A TAP EACH OF WHICH IS CONNECTED TO A CORRESPONDING TERMINAL OF A DIFFERENT ONE OF SAID UNIDIRECTIONAL ELEMENTS; MEANS CONNECTING EACH OF SAID BINARY ELEMENTS TO THE TAP CONNECTED TO SAID CORRESPONDING TERMINAL OF A CORRESPONDINGLY NUMBERED UNIDIRECTIONAL ELEMENT; MEANS TENDING TO DIVERT CURRENT FROM SAID SERIES CIRCUIT INTO SAID TAPS CONNECTED TO BINARY ELEMENTS IN SAID FIRST STATE; AND 